Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
As data transfer speeds have increased, high-speed differential serial lines have replaced large parallel buses in many designs. A Serializer/Deserializer (SERDES) converts parallel data into differential serial data, and differential serial data into parallel data. The interfacing requirements between a parallel data bus and a SERDES IC on a printed circuit board are implemented by a Protocol Controller device. In the transmission of data, transceivers send and receive packets of data on serial data lines. The protocol controller creates or “frames” these packets, which are then sent to the SERDES for transmittal to the data processing logic or memory.
Digital and mixed-signal design typically involves the use of one or more clock signals to synchronize elements across the system. For example, in synchronous digital systems, including board level systems and chip level systems, one or more clock signals are distributed across the system on one or more clock lines. However, due to various problems such as clock buffer delays, high capacitance of heavily loaded clock lines, and propagation delays, the rising edges of a clock signal in different parts of the system may not be synchronized. The time difference between a rising (or falling) edge in one part of the system with the corresponding rising (or falling) edge in another part of the system is referred to as “clock skew”.
Clock skew can cause sampled data systems to malfunction. For example, it is common for circuits in digital systems to have a first flip-flop output driving a second flip-flop input. With a synchronized clock on the clock input of both flip-flops, the data in the first flip-flop is successfully clocked into the second flip-flop. However, if the active edge on the second flip flop is delayed by clock skew, the second flip-flop might not capture the data from the first flip-flop before the first flip-flop changes state.
Delay lock loops are used in digital and mix-signal systems to minimize clock skew. Delay lock loops typically use delay elements to synchronize the active edges of a reference clock signal in one part of the system with a feedback clock signal from a second part of the system. As discussed and illustrated in U.S. Pat. No. 6,775,342, a conventional delay lock loop (“DLL”), which includes a delay line and a phase detector, receives a reference clock signal and drives an output clock signal. The delay line delays the reference clock signal by a variable propagation delay before providing the output clock signal. Thus, each clock edge of output clock signal lags a corresponding clock edge of reference clock signal by a certain propagation delay. A phase detector is then used to detect the associated phase difference and to control the delay line over a designated time span ranging from a minimum propagation delay time to a maximum propagation delay time.
Skew in the output clock signal can be caused by delays in various circuits such as clock buffers or propagation delays on the clock signal line that carries the output clock signal (e.g., due to loading on the clock signal line). To distinguish and recover the output clock signal from the skewed version of output clock signal, the skewed clock signal is routed back to a delay lock loop in a feedback path.
The DLL's phase detector controls a delay line to regulate the propagation delay. The actual control mechanism for the DLL can differ. For example, in one version of DLL, the delay line starts with a propagation delay that is equal to a minimum propagation delay, after power-on or reset. The phase detector then increases the propagation delay until the reference clock signal is synchronized with the skewed clock signal.
After synchronizing the reference clock signal and skewed clock signal, the DLL monitors the reference clock signal and the skewed clock signal and adjusts the amount of propagation delay to maintain synchronization. For example, if propagation delay increases, perhaps caused by an increase in temperature, the DLL would decrease the propagation delay to compensate. Conversely, if the propagation delay decreases, perhaps caused by a decrease in temperature, the DLL would increase the propagation delay to compensate. The time in which the DLL is attempting to first synchronize the reference clock signal and skewed clock signal, is referred to as lock acquisition. The time in which the DLL is attempting to maintain synchronization is referred to as lock maintenance. The value of the propagation delay at the end of lock acquisition, i.e. when synchronization is initially established, is referred to as initial propagation delay.
As explained above, the DLL delay line can only provide a propagation delay between a minimum propagation delay and a maximum propagation delay. During lock maintenance, the DLL may lose synchronization if a propagation delay smaller than the minimum propagation delay is required to maintain synchronization. Similarly, synchronization may be lost if a propagation delay greater than the maximum propagation delay is required to maintain synchronization.
To maintain this important signal (frequency) synchronization after lock acquisition, various approaches have been employed. These approaches include, for example, modifying the above-described DLL approach, in accordance with the above-referenced patent document, with the use of a clock phase shifter in addition to the delay line to synchronize the reference clock. The increased flexibility provided by the clock phase shifter increases the range of frequencies at which the DLL will operate.
Another synchronization approach is provided by a phase-locked loop (“PLL”) circuit. A common PLL circuit includes a signal phase-frequency detector, a low-pass filter, and a voltage-controlled oscillator (VCO). Normal operation of the PLL occurs in the above-described synchronization maintenance mode, that is, when the VCO frequency is near the incoming frequency. The phase frequency detector generates a signal that indicates if the frequency of the feedback from the VCO is too fast or too slow, and if the phase of the feedback is early or late, compared to the reference clock frequency and phase. The phase frequency detector output signal is integrated by the loop filter to generate the VCO control voltage. This voltage is used to control the VCO output frequency and phase.
An example of a particular PLL circuit that is useful for integrated circuit design is described and illustrated in U.S. Pat. No. 6,542,040 (Austin H. Lesea). This PLL circuit has a relatively wide range of oscillator output frequencies and a relatively wide range of loop divider values. This circuit is advantageous for implementation in integrated form because the total capacitance of its loop filter is small. The PLL includes two phase detectors, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. The oscillator output can be fed back via the loop divider to the first phase detector. The oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control and the programmable loop filter are controlled to realize the selected loop filter and the selected loop filter is switched into a control loop involving the second phase detector. The control loop controls the oscillator to achieve phase lock by varying a supply voltage (or current) supplied to the oscillator.
The electrical characteristics of such PLLs, however, vary over numerous operational conditions including operating frequency, divider value (M), supply voltage VDD, temperature, and process variations. Moreover, PLLs “lock” over a finite range of frequencies, given a particular value of M and a particular loop filter.
As with many other logic blocks, features provided by both PLLs and DLLs can be useful in an FPGA. Apart from frequency synchronization, a PLL can also be useful in a FPGA, if, for example, the PLL is used to do parallel-to-serial conversion. The PLL's output frequency ranges and the selected M may vary widely from user design to user design and, in an FPGA, can be controlled by the user. However useful they might be, FPGA implementations that include both a PLL as well as a DLL can bring with them the above-discussed inherent complexities and potential issues. When these circuits are implemented in FPGAs, other skew-causing variables are introduced and need to be controlled for the integrity of the system.
To address the issues of clock skew and clock distribution, systems designers typically use discrete clock distribution or clock synthesis components in their systems. These discrete components may use DLLs and PLLs to implement the required functions. These components do add cost to the overall system and have limited configurability and adaptability.